The present invention relates to a semiconductor device having a high operation speed and low power consumption and a method of manufacturing the same and, more particularly, to a semiconductor device having a semiconductor layer with a tensilely strain or compression strain applied to its interior or surface and a method of manufacturing the same.
Along with today""s size reduction of electronic devices and information terminals, a strong demand for reducing power consumption of electronic devices without lowering the operation speed has arisen. Reduction of power consumption of any electronic devices, to say nothing of portable information devices, is a great challenge from the viewpoint of preservation of the environment and energy resources.
A conventional electronic circuit uses bulk Si as a substrate and have met the above requirement by reducing the device size. However, miniaturization of a device has a physical and economical limitation, and a technique of increasing the operation speed and reducing power consumption without miniaturization must be established.
The electron state near the Fermi level of n-type unstrained Si that is conventionally used for an electronic device such as a ULSI degenerate sixfold. For this reason, as shown in FIG. 1, electrons present in a certain valley (in a wave number space, the region of an equal-energy surface of electrons at the Fermi energy EF) are scattered to the remaining five valleys by phonons. Such valley scattering decreases mobility of electrons.
When a tensile strain is applied to a Si thin film in a plane parallel to a surface of a (001) substrate, the electron state having an energy near EF is separated into a ground state with double degeneracy and an excited state with quadruple degeneracy. When the electron distribution is not excessively deviated from the Fermi distribution (for example, when no high field is applied), most electrons stay in the ground state with double degeneracy. An inter-valley scattering of electrons exclusively occurs in the wave number space between the two valleys. As a result, the mobility in the direction of plane increases. Hence, when a Si layer to which, e.g., a tensile strain is applied is used for the channel of an n-MOSFET, operation at a higher speed than that of a conventional Si n-MOSFET can be expected.
On the other hand, when such a strained Si layer or a compressively-strained SiGe layer formed on a Si substrate is used as a hole channel, mobility of holes increases due to the decrease in hole mass or lifting of the degeneracy of the valence band, as is pointed out. Consequently, an increase in operation speed of a p-MOSFET or p-MODFET can be expected. In both cases, a high-speed operation more than Si can be expected even at a similar or lower operation voltage than that of a conventional Si device. This suggests possibility of simultaneously realizing high-speed operation and low power consumption.
Tensilely strained Si is obtained by epitaxially growing Si on a crystal having a lattice constant larger than that of Si. Usually, a lattice-relaxed SiGe buffer layer is grown on a Si substrate, and a Si thin film is grown on the buffer layer.
However, to obtain a lattice-relaxed SiGe surface having a low dislocation density, a buffer layer as thick as several xcexcm is required. If the buffer layer is thin, the compressive strain remains on the surface of the SiGe layer, which results in an insufficient strain amount or dislocation density becomes very high though lattice relaxation is sufficient.
However, formation of a thick buffer layer requires a very long time of several ten minutes to several hours. Therefore, a problem arises in that the throughput decreases or large amounts of source gas are consumed. Furthermore, when a strained Si MOS region and a normal Si-MOS region are to be formed on one substrate, a large step of several xcexcm is generated due to the thick SiGe buffer layer. This makes a process such as lithography or electrode formation difficult.
In recent years, a technique of forming MOSFETS on an SOI substrate is used to decrease the parasitic capacitance and increase the operation speed. A thick SiGe buffer layer does not match this technique. In addition, when a SiGe buffer layer is made thick, the p-n junction area increases to increase the parasitic capacitance, so the SOI substrate is useless.
Especially, in manufacturing an integrated circuit, the requirement becomes more serious in terms of yield and uniform characteristics. The dislocation density need be suppressed to 1.0xc3x97103 cmxe2x88x922 or less. However, in the conventional technique, the dislocation density on the SiGe buffer layer surface is as high as 104 to 107 cmxe2x88x922, and an integrated circuit is difficult to realize.
As described above, when a thick SiGe buffer layer is formed, the throughput decreases and large amounts of source gas are consumed. Therefore, manufacturing cost increases. In addition, since a large step is generated in the thick buffer layer, the process such as lithography or electrode formation is difficult.
The dislocation density of the buffer layer must be suppressed to 1.0xc3x97103 cmxe2x88x922 or less. However, the dislocation density on a SiGe buffer layer obtained by the conventional technique is as high as 104 to 107 cmxe2x88x922, and an integrated circuit is difficult to realize.
It is an object of the present invention to provide a semiconductor device which has a strained semiconductor layer applied with a tensile or compressive strain, and also has a low dislocation density and a sufficiently thin buffer layer, and is capable of realizing high-speed operation and low power consumption, and a method of manufacturing the semiconductor device.
In order to achieve the above object, according to the first aspect of the present invention, there is provided a semiconductor device comprising: a first semiconductor layer; a second semiconductor layer formed on the first semiconductor layer, wherein the second semiconductor layer has an uneven surface and has a lattice constant different from that of the first semiconductor layer; a buffer layer formed on the uneven surface of the second semiconductor layer; and a strained semiconductor layer formed above the buffer layer, wherein the strained semiconductor has a lattice constant different from that of the buffer layer.
According to the second aspect of the present invention, there is provided a semiconductor device comprising: a Si1-xGex (1xe2x89xa7x greater than 0) layer formed on a silicon substrate, wherein the Si1-xGex layer has an uneven surface; a Si1-yGey (xxe2x89xa0y) buffer layer formed on the uneven surface of the Si1-xGex layer; and a strained Si1-zGez (zxe2x89xa0y) layer formed above the Si1-yGey layer.
Preferably, x greater than y greater than z, or x greater than y and z greater than y.
The average film thickness of the Si1-xGex (1xe2x89xa7x greater than 0) layer is preferably 1 to 5 nm.
The Si1-zGez layer is used as a channel of electrons or holes.
According to the third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming, on a first semiconductor layer, a second semiconductor layer having an uneven surface and a lattice constant different from a lattice constant of the first semiconductor layer; forming a buffer layer in an amorphous state on the uneven surface of the second semiconductor layer; annealing the buffer layer in the amorphous state to crystallize the buffer layer; and forming a strained semiconductor layer above the buffer layer.
The second semiconductor layer having an uneven surface is formed in the so-called Stranski-Krastanov growth mode in which islands are sponstaneously formed so as to relax lattice mismatching with the semiconductor substrate.
The present invention with the above arrangements has the following functions and effects.
When the second semiconductor layer having an uneven surface is formed on the first semiconductor layer, stresses are accumulated in the boundary region between convex portions, so crystal defects can be generated around the region. When the buffer layer in the amorphous state is deposited on the resultant structure and annealed, crystallization starts from a region in contact with the second semiconductor layer. A strain energy is accumulated as crystallization progresses. When the strain energy exceeds a certain critical value, dislocation is generated near the boundary region from the interface between the crystal layer and amorphous layer toward the second semiconductor layer.
When crystallization further progresses, due to the above dislocation, dislocations parallel to the substrate grow between convex portions. The generation of the threading dislocation reaching the surface of the crystal layer is suppressed due to the dislocation network generated in the island structure region parallel to the substrate at a high density. Since the lattice constant difference between the buffer layer and first semiconductor layer is absorbed by the dislocation, a sufficiently relaxed buffer layer having a low dislocation density can be obtained.
If the buffer layer is directly formed by an epitaxial growth on the second semiconductor layer having an uneven surface, the surface of the buffer layer also could be uneven, and a process for planarizing the surface is required. However, as in the present invention, by the deposition of the amorphous buffer layer and the subsequent annealing, a crystalline buffer layer having a flat surface can be obtained because the uneven structure is not reflected on the amorphous structure.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.